The present invention relates generally to substrate structures and more particularly to a low temperature co-fired ceramic substrate structure having a dual use buried layer.
Various type of dielectric materials are used for forming substrates for electronic applications. One common material used for substrates is an alumina ceramic material with conventional thick or thin film resistors and metallization formed on the top surface of the substrate. Alumina ceramic substrates have the advantage of being thermally conductive, which aids in the dissipation of heat generated by integrated circuit devices mounted on the substrate. A drawback to alumina ceramic substrates is the inability to form interior layers in the substrate.
Low temperature co-fired ceramic (LTCC) material is also used for forming dielectric substrates for electronic applications. The advantage of LTCC material is the ability for form buried components, such as resistors, capacitors, inductors, transformers and the like within the substrate. U.S. Pat. No. 5,604,673 teaches a low temperature co-fired ceramic substrate for power converters. The low temperature co-fired ceramic substrate includes a number of layers with various metallized conductors located on the outer surface and various inner layers of the substrate. A cavity into which an integrated circuit is placed may be formed with or without thermal vias being formed in the substrate immediately beneath the cavity. A heat sink is positioned underneath the substrate that mates with the thermal vias to provide thermal management for the electronic circuit formed on the substrate. Alternatively, the integrated circuit device may be positioned on the top surface of the substrate with thermal vias formed beneath the substrate location. A cavity is formed in the substrate from the opposite side of the substrate that receives a heat sink. The heat sink mates with the thermal vias underneath the integrated circuit device for thermal management. A further alternative is to form an in-situ heat sink in the low temperature co-fired ceramic substrate using high thermal conductivity LTCC tape as described in U.S. Pat. No. 5,386,339. A portion of the low temperature co-fired ceramic substrate under the integrated circuit is replaced with the high thermal conductivity LTCC tape.
Various strip line components and passive devices are formed in the low temperature co-fired ceramic substrate as required by the particular circuit design. For example, a capacitor may be formed by locating two parallel conductive plate structures adjacent to each other and separated by a low temperature co-fired ceramic layer in between. Conductive vias may be used to connect the plates to components on the surface of the substrate on other buried components in the substrate.
A drawback to the above described co-fired ceramic structures is providing the proper voltages to the integrated circuit device while providing thermal management of heat generated by the device. Generally, surface mounted IC devices have their bottom surface acting as a voltage input lead. The prior art teaches coupling this lead to a ground potential through the heat sink and vias. However, in certain applications the voltage input lead on the bottom of the IC needs to be at some voltage level, such as a negative source voltage. Therefore, there is a need for a LTCC substrate structure that allow the bottom surface voltage input leads of an IC to be coupled to a non-electrical ground voltage supply while maintaining the heat sink at ground potential to provide thermal management of the heat generated by the IC device. Such a structure should have a minimal effect on the overall size of the substrate. The substrate structure should also provide flexibility in laying out and connecting various components formed on and in the substrate structure. Further, there is a need to combine elements of the thermal management structure with the component structures for maintaining a minimum size for the substrate.
Accordingly, the present invention is to a low temperature co-fired ceramic substrate structure having first and second dielectric layers with top and bottom surfaces. The top surface of the first dielectric layer has a first conductive pattern formed thereon having a first conductive element functioning as a first plate of a capacitor. A second conductive element formed on the top surface functions as a voltage potential lead for an integrated circuit device where the bottom surface of the integrated circuit device is a voltage input lead for the integrated circuit device. A second conductive pattern is disposed between the first and second dielectric layers and positioned below the first conductive pattern to function as a second plate of the capacitor and as a thermally conductive heat transfer layer for the integrated circuit device. At least a first thermally conductive via is formed between the top and bottom surfaces of the second dielectric layer and below the second conductive element on the top surface of the first dielectric layer. The via is thermally coupled to the second conductive pattern.
Preferably, the substrate structure has a plurality of thermally conductive vias formed beneath the integrated circuit device in an array pattern. A heat sink may be disposed adjacent to the bottom surface of the second dielectric layer and thermally coupled to the thermally conductive via or vias. In the preferred embodiment of the invention, a third conductive pattern is formed on the bottom surface of the second dielectric layer that is thermally coupled to the thermally conductive via or vias. The heat sink is disposed adjacent to the bottom surface of the second dielectric layer and thermally coupled to the third conductive pattern. The thermally conductive via or vias are preferably cylindrically formed bores filled with a high thermally conductive material, such as gold. It is also preferred that the thermally conductive via or vias be electrically conductive.
The first dielectric layer preferably has a thickness approximately 0.004 inches and the second dielectric layer has a thickness approximately 0.025 inches. The conductive patterns have a thickness approximately 0.0005 inches. Each of thermally conductive vias in the array have a bore diameter approximately 0.010 inches and a center to center spacing approximately 0.020 inches.
The objects, advantages and novel features of the present invention are apparent from the following detailed description when read in conjunction with appended claims and attached drawings.